Analog-to-digital converter

ABSTRACT

An equilibrium type coder comprising an array of multistable and weighted stages interconnected with each other and the analog input to provide an input signal to each stage including the analog signal and weighted functions of the output signal of each stage. The weights of each stage as provided by weighted interconnects, or different biasing of the stages are such that the array has a plurality of stable states each corresponding to a different amplitude of the analog signal. The digital representation of the analog signal is provided by the state of the stages when the array is in a stable state.

United States Patent Fluhr [72] Inventor Kenneth William Cattermole 3,100,298 8/1963 340/347 Harlow, England 3,1 19,105 1/1964 Jepperson 340/347 [21] Appl. No. 700,874 3,225,347 12/1965 Doyle 340/347 [22] Filed Jan. 26, 1968 3,255,447 6/1966 Sharples 340/347 [45] Patented May 18, 1971 mary ExammerMaynard R. Wilbur (73] Abslgnee standard Elecmc Assistant ExaminerGary-R. Edwards Attorneys-C. Cornell Remsen, J r., Rayson P. Morris, Percy New York, N.Y. [32 1 Priority Feb 10 1967 P. Lantzy, Phlllp M. Bolton and Isidore Togut 1 [33] Great Britain [31] 6509/67 E ABSTRACT: An equilibrium type coder comprising an array [54] ANALOGTGDIGITAL CONVERTER of multistable and weighted stages interconnected with each other and the analog input to provide an Input signal to each 10 Claims, 11 Drawing Figs. r stage ll'lCllldlIlg the analog signal and weighted functions of the E g-S-il optput of each stage The weightof each as pro.

H03k13/17 vided by welghtedmterconnects, or different biasing of the of tages are uch the array has a of stable tates 1561 References Cited 3E;iii: 55512758512ZJiiifiifiiii'ifihfifi $3125 UNITED STATES PATENTS vided by the state of the stages when the array is in a stable 2,754,503 7/1956 Forbes 340/347 state.

I 0/ I /je/ r 292 R3 Mulc/sto-b/e Dev/ ces a X a (Fl/ 1 7322 83 fla/og. ,4 flgna/ "1 WW? X is? air/e2 l w ANALOG-TO-DIGITAL CONVERTER BACKGROUND OF THE INVENTION This invention relates to analog-to-digital converters such as used in pulse code modulation (PCM) systems of communication.

SUMMARY OF THE INVENTION An object of this invention is to provide an improved analog-to-digital converter of the equilibrium type.

A feature of this invention is the provision of an analog-todigital converter comprising an analog signal input; and an array of multistable and predeterminedly weighted stages interconnected with each other and the analog signal input to provide an input signal for each of the stages including in combination the analog signal and a weighted function of the output signal of each of the devices; the weights of each of the stages having a predetermined value to provide a plurality of stable states for the array, each of the stable states corresponding to a different amplitude of the analog signal; the digital representation of the analog signal being provided by the state of the stages when the array is in a stable state.

The term multistable device or stage as used in this specification and claims means a device or stage having two or more stable conditions. The term weight as used in this specification and claims means an arithmetical factor by which an energy value may be multiplied and a weight may have a positive or negative value or may be zero.

BRIEF DESCRIPTION OF THE DRAWING The above mentioned and other features and objects of this invention will become more apparent by reference to the following drawings, in which:

FIG. 1 is a block diagram illustrating the basic arrangement of one type of converter according to the principles of this invention;

FIG. 2 is a block diagram illustrating a modified version of the converter of FIG. 1;

FIGS. 3a to 3h are a set of operating sequence diagrams illustrating the operation of the converters shown in FIGS. 1 and 2; and r FIG. 4 is a block diagram of an alternative type of converter according to the principles of this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The converters illustrated in the FIGS. employ one basic type of circuit, referred to herein as binary discriminators or bistable devices. A typical discriminator is derived from a pair of similar transistors having their emitters coupled together, the input to the circuit being to one of the transistor bases, the other base being fed with a bias signal. An out or outputs can be taken from either or both collectors. Such a circuit is commonly known as a long-tail pair. Modifications to the basic discriminator circuit are quite straightforward and will be described when required.

The converter shown in FIG. 1 consists essentially of a number of multistable devices, bistable devices, or discriminators D1, D2...Dn, one for each digit, an input amplifier A and an interconnection and feedback matrix having a plurality of weighting resistors 1R1, 1R2, 1R3...nR1, nR2, nR3 etc. Each discriminator gives a binary output a, whose value depends on the sign of the input in to that discriminator.

The input analog signal is first amplified and the output of the amplifier A is termed x, and x will henceforth be regarded as the input to the converter. The input x is applied via the weighting resistors XR], XR2, XR3, to the discriminator inputs. The input to discriminator D1 is now x, and so on, and the output of that discriminator becomes a, and so on. The outputs a ...a,, are coupled to the inputs via the relevant weighting resistors and so feedback is introduced.

It has previously been said that the arrangement of multistable devices, i.e. binary discriminators, is capable of holding one of a number of combinations of stable states, the particular stable state arrived at being one unique to the value of the analog input signal at that time (neglecting the small delays inherent in the circuits). Therefore, it must be established that:

i. It is possible to couple the digit devices in such a way that the only stable states are those giving a correct and complete encoding.

ii. It is possible to choose the dynamic properties of the digit devices in such a way that, whatever the initial conditions, the encoder proceeds through an autonomus sequence until it reaches the correct state, and then stops.

This will be proved by defining a mechanism which does it.

We start by deriving from the basic properties of quantization a general condition which must be satisfied by an encoder using weighted digits: this includes equilibrium encoders.

Let a set of N unit intervals (quanta) be defined by n digits a,- each of which has a weight w,. An input signal it is quantized to the next lower integer [x] which equals the weighted sum of digits.

Then: x1 Zaiwr$x (1) The summation being taken over all the digits. Next, distinguish one digit a, and derive a relation between this digit and all the other quantities. It follows from equation (1) that:

w1-Z .wi .w.SwZ 1wi (2) where the symbol 2 denotes a partial summation omitting the term in 0,.

Now a, is a binary variable and takes the values 0 and I only. The left-hand inequality is strongest when a =0. In this eventx 1 Za -w.- 0 But when a,=0 the partial and complete summations differ only in a zero term, and so:

xI2a w, O (a ,=0). (3) The right hand inequality in equation (2) is strongest when a,=l. In this event x E m-w,- r But when a =l the partial and complete summations differ by w,, and so X 2ai i r Inequalities (3) and (4) may be written in the common form:

wm r Z i i 2 0 F Thus, for each digit a, there is defined a function x,.,, of the input x and the digits a, whose sign depends on the value of a Consider the binary-number code, in which the weights are successive powers of two. The fundamental condition of equation l can then be written as the summation being taken over all n digits. This expresses the fact that the n digits divide the range into 2" unit intervals. Now it is equally true that the first j digits divide the range into 2" intervals of magnitude 2" For instance, the first digit divides it into two halves (each 2" units): the first and second, into four quarters (each 2" units): and so on. This may be expressed in a form homologous with equation (6),

or, dividing throughout by 2"- a: 3 x EI 8) It follows, by a process exactly parallel to the derivation of equation (5), that:

i %-a. 2 a-,2 0(a,=0)

Z 0(ar= 1) (9) for the first j digits only, i.e. r j. The term 5,. is the complement of the digit a,. Multiplying by 2" gives the equivalent form.

for the first j digits, defining a funfi5i,,wi; s sign depends on the value of a Consider an arbitrary digit a,. By taking successively j=r, r+l ...n there-is obtained n-r+l pairs of inequalities similar to equation (10). One of these, namely for j=n, is the same as equation (5) withthe weight values w =2". One digit, namely the last, has this pair and no otherz'for all the other digits a choice is available. Now it may not be obvious at first sight which of the possible relations is the most significant. It will be shown later on that each of many different sets of relations specifies the essential properties of a different encoding mechanism. In particular, two mechanisms which will be described in some detail are specified respectively by choosing the relations:

Type 1 j=n in equations Type 2 j=r in equations 10).

The functions so defined are, respectively,

n rr -ar (132" I rr ar2 2 a 2 rl J =..w--2-" a 2 It follows from theiinequalities (10) that if x, denotes either x,,, or in. then I a.=o)

The set of inegualities (13) suggests an encoding "mechanism and defines its stable states. An equilibrium encoder was defined above as an array'of .multistable devices,

I one per digit, suitably coupled to each other and to an input signal. Take the digit ilevices to be binary discriminators; each one gives a binary output a, whose value depends on the sign f th t th o empu x, us i if i The couplings may Bribe represented by taking for each x,' a weighted sum of allgthe digit outputs a -and of the input signal 1;, as in the block diagram of FIG. I. The connections at the crosspoints of the ariatrix symbolize weighting resistor networks, such as are commonly used in decoders, summing amplifiers etc. a:

In terms of this mechanism, the inequalities (5), (l0) and 13) suggest the usegdfthe functions at or-x 'as discriminator inputs. Considering -zjirst the Type I encoder. the weighting matrix is a2= x,,. x Ea,w, -"i,' (15) where E, is the complement of the digit a,. Now the first two .terms are common *to all digits, so that the block diagram of FIG. 1 can be simplified to the block diagram of FIG. 2, using weighting matrix WM as defined in equation (15) to generate the first two terms only and producing Z, by local feedback in each discriminator. it

The converter of FIG. 2 uses the same'basicdiscriminators D1...Dn as the con-letter of FIG. 1 but they are now assumed to have been modified to have differential inputs, which is .easily arranged. Bygproviding a resistor coupling between the bias inputto the long tail pair and-the collector of the other transistor the discriniinator is turned into a bistableIflip-flop, or Schmitt trigger circuit. The feedback connection provides in each discriminator the individual term E, in equation (15). .Each discriminator in FIG. 2' has a hysteresis of 1 quantum on the amplitude scale.

This encoding mechanism embodies inequalities .which are entailed by the basic encoding rule, and, therefore, it is expected to have stable-states which represent a correct encod- :ing of the input. It isless obvious that .these are the only states, 'but it is possible to provexthisby arranging the'previous argument backwards. First, consider an arbitrary input x to be correctly encoded; so that equation 1 issatisfied. Then:

and, hence, from equation (15) :But, by the property of equation 14) of the binary discriminabinary values a and so this state is stable. Now let x be changed until equation (16) is violated, which means that the encoding is no longer correct. If x is too great, so that x Ea;w, 1, then x, 0 for all r. Thus, any units in the binary 0 condition are driven to the binary 1 condition. If-x is too small, so that x Za w; l, then x,20 for all r. Thus, any units in the binary 1 condition are driven to the binary 0 condition. Thus, a state which represents an incorrect encoding is not. stable and cannot persist.

So far, it has not be necessary to specify the weights w All the above reasoning with respect of the Type I encoder applies to any weighted code. With weight allocations corresponding to a redundant code, these may be alternative characters which make up the same weighted sum and further constraints would be needed to ensure that the right one were chosen every time. This complication does not arise with the binary-number code, for which F' and there is a unique'set of digits a, for every possible sum.

One form of misbehaviour, namely, stability in wrong states, has been proven not to occur. The other possible form, namely, persistent instability, can be eliminated by a correct choice of dynamic properties. It is easy to see what must not be allowed to happen. Suppose that all the digit discriminators would respond simultaneously. Then any input x above the first threshold would turn them all on. Unless at were also above the last threshold, .thefeedback would then turn them all off again, and so on. I

By an extension of this argument, it may be shown that no two digits may-be allowed to consistently switch simultaneously. For example, suppose that x 2a w, x+h, l 8) where h is a positiveinteger and that the resulting negative x, cause two or more digits .to change from 1 to O, diminishing the weighted sum by h+1. The x now becomes positive,'tending to change the digits from-0 back to 1. If the same combination reverts simultaneously, the original state is restored. Now,

for two ormore positive integral weights, their sum must be at to a sustained input only after a delay t, and it does not respond at all to an input'signal shorter than t It is still possible for a step in the input to cause several digits to change (not simultaneously, but in quick succession) and the weighted sum to overshoot. But whenthereversal occurs, the first digit to go back differs from the last one to go forward, and so'the oscillation between two wrong codes differing in several digits is avoided.

Oscillation of a single digit must also be prevented, and this suggests the choice of delays t Instability can occur if h+lZ2 (see inequality (18) and ensuing discussion) and, hence,'a single weight of 2 or morecan be switched on and off repeatedly. Therefore, a digit controlling such a weight must never be the first digit to change: the digit with weight 1 must have a'faster response than any other.

Consider now a specific case which uses:

i. Binary weights according to equation 17).

ii. Quantized response times ranging from T to nT.

Thus:

t,=(Ni+1 T 19) The encoding operations then follow a sequence drawn from a repertoire which will now be defined..First choose a I notation. Let the binary number. a a ...a,,' be notedby y, and

tors, these inputs are such as to'lock themin their respective the encoding-is to-be correct, then y,=[]. It will be shown that the sequence coverges to a correct encoding, and that an upper bound to the number of time intervals is:

831/2 n(n+l) (20) As a concrete illustration, consider an 8-level encoder with weights 1, 2 and 4. Its sequences starting from y =0 and converging to y,=0, l, 2...7 are shown in FIG. 3a. The principle governing these sequences is:

i. If y y,, then each of the weights are ofif (a,=0) and turn on in the order 1, 2, 4 with delays T, 2T, 3T respectively. ii. If y y,, then each of the weights as are on (a,=l) and turn off in the same order.

The delays are measured from the instant when the discriminator input x, changes sign. For instance, with y,,=0 and y,=[x] 24. all digits change from 0 to l at times T. 2T. 3T for digits 3, 2, 1, respectively. If also y, 7, the result is an overshoot which reverses x and x at time 3T: digits a a change back to O with further delays T, 2T. With y, 4, digit 1 does not change since it having moved positively at t=0, becomes negative again before the delay 3T has elapsed.

It is fundamental to the present encoder that the initial condition need not be defined. It will converge to any encoded value y, from any starting-point y,,. The remainder of FIG. 3 shows the sequences starting from y =l, 2...7, respectively. Actually, there is no need to work out sequences for the last four values, since it is obvious from the rules that they are complementary to the others. The diagram displays this clearly. The greatest value of s is 6, in accordance with the inequality (20). This is attained for y,=l (in binary-number form) with y =0xxx and for y,=0l0 with y,,=lxx. It is clear from the diagram that these are the worst cases because every possible overshoot occurs. To obtain the first digit, the largest weight has to be reversed which takes 3T. To obtain the second digit, the next largest weight has to be reversed again which takes 2T, and so on. This result is easily generalized. With an n-digit binary-number code and initial condition a a a the longest sequence is the one leading to y =fiiaifirar 271m since every digit must be reversed in descending order of weight. The time taken, as a multiple of the unit T, is s=n+ (n--l +(n-2) +...+l=p(n+). (21) No other sequence is as long as this, and so the inequality is proven.

This time is of course a rather large multiple of the unit time T, but T itself, which is basically the time needed to make a binary decision, can be short. The digit period of a normal sequential encoder needs to be of the order nT, given the same basic devices, so that its encoding time is n T which is greater than the maximum sT quoted above.

The type 2 encoder uses as discriminator inputs the functions x as defined in equation (12). FIG. 4 shows the essential parts of such an encoder. In this embodiment each digit is generated by a stage consisting essentially of a discriminator D1, D2 etc. and an adder A1, A2 etc., the stages being connected together in a tandem structure. Each stage, as shown, receives as its input the combination of a weighted function of the inputs and a weighted function of the output from each previous stage only. It may be thought at first sight that the arrangement of FIG. 4 is in conflict with the previous statement that each discriminator input is a combination of a weighted function of the input and a weighted function of each output from all the other discriminators, but this is not so. In the case of FIG. 4 the weight assigned to the output of any succeeding stage is zero, hence, a simplified arrangement compared with FIG. 1, for example.

The discriminators of FIG. 4 are basically the same as those of FIG. 1, i.e. a long-tail pair, with the difference that the bias applied to each discriminator is detemiined by its weight. I-Ience, D1 is subjected to a bias voltage 2", D2 has a bias voltage 2", and so on. The output from each discriminator is then taken, together with the input to that stage, to a weighted adder where the two values are added and weighted to provide the input for the next stage. It is easily verified that the input x, to discriminator D,. is identical with x as defined above.

It is clear from the derivation that states which represent a correct encoding are stable, but it is not immediately obvious that they are the only stable states. If the input 2: is correctly encoded, then equation (7) is satisfied (in particular, for j=r) By the property of the binary discriminators, expressed in equation these inputs are such as to lock them in their respective binary values, and so this state is stable. Now let x be changed so that the encoding is incorrect. Then equation (22) is violated, at least for some value of r. First, let x be reduced until the left-hand inequality in equation 22 is untrue for some values of r. The x, 0 and, if a,- was in the 1 condition it is driven to the 0 condition. Which digit will be first affected? Clearly the one for which the summation in equation (22) is greatest, namely, the least significant digit which is in the 1 condition. Thus, an incorrect code whose weighted sum is too great is unstable.

If x be increased until the right-hand inequality in equation (22) is untrue for some value of r, then x30 and if a, was 0 it is driven to l. The digit first affected is most easily identified by rewriting equation (22) in terms of the digit complements fi As x increases, the left-hand inequality is first violated in respect of the digit for which the summation in equation (24) is greatest, namely, the least significant digit which is a 0. This digit is driven to l, and so an incorrect code whose weighted sum is too small is also unstable. The two parts of the proof taken together show that the only stable states represent correct encodings.

The operating sequence of this encoder is defined by the static properties, and the modes of instability which had to be eliminated in the first embodiment by choice of delay times do not arise. If the input be increased slowly then (i) as a threshold is traversed, the first weight which is required for the higher but not the lower level turns on. (ii) As this takes effect, the weighted sum overshoots the signal level and the first weight which is used in the lower level but is not required for the higher turns off. (iii) This process continues in a similar manner until the correct code is reached. The sequences are similar to those of the previously-described encoder even though they are determined by a different mechanism. There is no need to introduce any deliberate delay, and so the delay time of each digit unit may be as short as the devices and construction will allow. If it is supposed that any digit may be switched in the time T (as defined earlier) then the longest sequence occupies a time nT. The worst case is the same as for the previous encoder, namely, the generation of code 1010- from an initial state Oxxx-(or the complementary process). In the first interval all digits switch to 1. In the next interval, all but a revert to 0. Then all but a switch back to I again, and so on. The sequence is the same as in FIG. 3, except that successive transitions in the same direction are now simultaneous rather than staggered.

It should be noted that the various operations may overlap one another. It is not necessary to wait for the end of one operation before initiating another.

It will be seen that the structure shown in FIG. 4, comprises a number of tandem units, each of which (i) accepts an input signal, (ii) generates one more digit, and (iii) passes on a residual signal to the next unit.

The form of this residue follows from equation (12), which shows that Each unit comprises a discriminator D and weighted adder A. The residue constructed by A, is a a, ,+2"", so the discriminators need to be differential as previously described.

This structure is important because it shows clearly that the encoder is stable. A mechanism with multiple feedback loops,

as FIG. 1 or 2, is not obviously stable: proof of stability must be adduced. A. structure such as that of FIG. 4 which is equivalent to a chain with one-way propagation must be stable, and so whatever the dynamics of the individual units this form of equilibrium-seeking encoder cannot oscillate. The nature of the proof implies a condition: provided that the weight w, contributing to decision function x, is truly the same for all values of r i.

The basic theory leading up to the relation of equation gives n-r-l-l pairs of inequalities for the rth digit. Most of these have remained unused. Consider now how they are applicable to encoding structures.

As a generalizatiom of equation (11) or equation (12), it is possible todefine:

and linear combinations of these quantities, i.e.

where the values b' are non-negative and not all zero but otherwise arbitrarytfl'hese form a valid set of decision functions for an encodergyin that the stable states correspond to correct encodings.

The embodimenttof FIG. 2 follows from putting b =l and all other b=0. The embodiment of FIG. 4 follows from putting b and all other b=0. This is best illustrated by writing the coefficients b in a matrix, thus;

The restrictions onthe matrix of the generalized encoder are: (i) there must be at least one nonzero element in each row, and (ii) all nonzero elements must be on or above the leading diagonal.

While I have described above the principles of my invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of my invention as set forth in the objects thereofi and in the accompanying claims.

I claim:

1. An analog-todigital converter comprising:

an analog signal input; and

an array of multistable binary weighted stages interconnected with each other and said analog signal input to provide for each of said stages an input signal including in combination said analog signal and a binary weighted function of the output signal of each of said stages; the weights of each of said stages having a predetermined value to provide a plurality of stable states for said array, each of said stable states corresponding'to a different amplitude of said analog signal; the digital representation of said analog signal being provided by the state of said stageswhen'said array is in a stable state. 2. A converter according to claim 1, wherein: each of said stages include a multistable device. 3. A converter according to claim 2, wherein said multistable devices are bistable devices. 4. A converter according to claim 1, wherein said stages include a multistable device for each of said stages, and weighted interconnections to couple the output of each of said devices and said analog signal input to the input of each of said devices. 5. A converter according to claim 4, wherein said multistable devices are bistable devices.

6. A converter according to claim 5, wherein said interconnections provide an input signal to eachof said bistable devices equal to x2a,w;5,, where x is the value of said analog signal, ia W, is the summation of the .output digits a, of each of said bistable devices each of said digits a,- having a weight w, and a,- is the compliment of said output digits 0, of each of said bistable devices.

7. A converter according to claim 6, wherein each of said bistable devices include an input, an output, a complementary output, and

a feedback path between said complementary output and said input to provide the term 5, for said input signal x, thereto; and said interconnections provide the terms x-2 a,-w, of said input signal x, to. each of said bistable devices.

8. A converter according to claim 1, wherein each of said stages responds to an input signal applied thereto after a given time delay, each of said stages having a different time delay being arranged in the order such that said stage with the smallest weight has the shortest time delay.

9. A converter according to claim 1, wherein said stages are coupled in series relationship with respect to each other and said analog signal input;

the first of said stages including a multistable device coupled to said analog signal input,

and

an adding circuit coupled to said analog signal input and the output of said device;

the remainder of said stages except the last of said stages including:

a multistable device coupled to the output of the adding circuit of the immediately preceding one of said stages; and

an adding circuit coupled to the output of the adding circuit of the immediately preceding one of said' stages and said device of its stage; and the last of said stages include; a multistable device coupled to the output of the adding circuit of the immediately preceding one of said stages.

10. A converter according to claim 9, wherein each of said multistable devices include a source of different bias voltage to provide the desired weighting for each of said stages. 

1. An analog-to-digital converter comprising: an analog signal input; and an array of multistable binary weighted stages interconnected with each other and said analog signal input to provide for each of said stages an input signal including in combination said analog signal and a binary weighted function of the output signal of each of said stages; the weights of each of said stages having a predetermined value to provide a plurality of stable states for said array, each of said stable states corresponding to a different amplitude of said analog signal; the digital representation of said analog signal being provided by the state of said stages when said array is in a stable state.
 2. A converter according to claim 1, wherein: each of said stages include a multistable device.
 3. A converter according to claim 2, wherein said multistable devices are bistable devices.
 4. A converter according to claim 1, wherein said stages include a multistable device for each of said stages, and weighted interconnections to couple the output of each of said devices and said analog signal input to the input of each of said devices.
 5. A converter according to claim 4, wherein said multistable devices are bistable devices.
 6. A converter according to claim 5, wherein said interconnections provide an input signal to each of said bistable devices equal to x- Sigma aiwi-ar, where x is the value of said analog signal, Sigma aiWi is the summation of the output digits ai of each of said bistable devices each of said digits ai having a weight wi and ar is the compliment of said output digits ai of each of said bistable devices.
 7. A converter according to claim 6, wherein each of said bistable devices include an input, an output, a complementary output, and a feedback path between said complementary output and said input to provide the term ar for said input signal xr thereto; and said interconnections provide the terms x- Sigma aiwi of said input signal xr to each of said bistable devices.
 8. A converter according to claim 1, wherein each of said stages responds to an input signal applied thereto after a given time delay, each of said stages having a different time delay being arranged in the order such that said stAge with the smallest weight has the shortest time delay.
 9. A converter according to claim 1, wherein said stages are coupled in series relationship with respect to each other and said analog signal input; the first of said stages including a multistable device coupled to said analog signal input, and an adding circuit coupled to said analog signal input and the output of said device; the remainder of said stages except the last of said stages including: a multistable device coupled to the output of the adding circuit of the immediately preceding one of said stages; and an adding circuit coupled to the output of the adding circuit of the immediately preceding one of said stages and said device of its stage; and the last of said stages include; a multistable device coupled to the output of the adding circuit of the immediately preceding one of said stages.
 10. A converter according to claim 9, wherein each of said multistable devices include a source of different bias voltage to provide the desired weighting for each of said stages. 